1. Technical Field
The present invention generally relates to a clock generator and, more particularly, to a four-phase clock generator capable of providing the phase correlation between four reference clock signals according to an internal phase-locked loop (PLL) to perform timing sequence self-detection.
2. Description of Related Art
Clock generators have been widely used in various electronic devices, the main purpose of which is to provide accurate clock signals so that the electronic devices may operate with reference to the accurate clock signals. Most of the currently available clock generators employ phase-locked loop (PLL) circuits.
Furthermore, the PLL is a synchronization technology based on the feedback signal so as to synchronize the frequency and the phase of the output signal with the frequency and the phase of the external reference signal. In other words, the PLL synchronizes the output signal with the external reference signal so that the output signal and the external reference signal have the same frequency and the same phase.
More particularly, when the frequency or the phase of the reference signal changes, the PLL detects such change and adjusts the output signal according to the internal feedback signal until the output signal synchronizes with the reference signal. The synchronization process is referred to as “being locked”. As stated above, the PLL is essentially a closed loop system. Under the control of the feedback signal, the PLL generates clock signals with high accuracy.
However, when the feedback parameters in the PLL are used to change the frequency of the clock signals generated by the clock generator, the PLL requires an additional period of settling time.
To effectively avoid the settling time, the PLL has been used with a digital logic circuit as a new type of clock generator. In such clock generators, the frequency of the output signal from the PLL is first fixed and then changed by the digital logic circuit so that the clock signals output from the clock generator have a frequency that has been changed.
Unfortunately, since the following digital logic circuit is an open loop system, the clock generator is easily affected by noise. As a result, the timing sequence of the clock signals from the clock generator can be incorrect.